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High-Performance Combined Data/Address Memory Test

IP.com Disclosure Number: IPCOM000102585D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 5 page(s) / 206K

Publishing Venue

IBM

Related People

Arimilli, LB: AUTHOR [+3]

Abstract

There are two parts to a memory test. One part should test the RAM cell integrity (data test) and the other part should test for address errors. The RAM cell integrity test is a test of each RAM cell to check if it can successfully store a '0' value and a '1' value. The address test is to check if there are address errors, such as address coupling or address lines that are stuck low or high.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 27% of the total text.

High-Performance Combined Data/Address Memory Test

       There are two parts to a memory test.  One part should
test the RAM cell integrity (data test) and the other part should
test for address errors.  The RAM cell integrity test is a test of
each RAM cell to check if it can successfully store a '0' value and a
'1' value.  The address test is to check if there are address errors,
such as address coupling or address lines that are stuck low or high.

      To test the RAM cell integrity, a '0' is written to every
location and read back to check that it is still a '0'.  Similarly, a
'1' is written to every location and read back to check that it is
still a '1'.

      To test for address errors, a pattern is written into memory.
As the pattern is read and tested, its complement is written in its
place.  If there is address aliasing, then the complement of the data
will be read.

      The method presented here combines the data test and address
tests described above.  The combined test is faster than the separate
test with the same test coverage.  The proposed IPL ROS test which
uses the combined data/address method is shown below.

      An ECC word in our system consists of 40 bits of which 32 are
data bits, 7 are check bits, and one is a spare bit (for
bit-steering). The following two ECC words will toggle all of the
memory bits.  In the RISC System/6000* there is a test mode that
writes data bit 0 into the spare bit and compares the spare bit to
data bit 0 during reads. In this test mode, if data bit 0 does not
match the spare bit, then an error will be flagged.  This discussion
is based on the test mode being enabled.
          Data Bits (hex)   Check Bits (binary)  Spare Bit
             AAAAAAAA           1001111              1
             55555555           0011111              0

      Although all the data bits and the spare bit will be toggled,
not all of the check bits will be toggled.  To toggle the check bits
that will not be toggled by the above ECC words, either of the
following ECC words can be used (we use both to toggle the maximum
number of bits).
          Data Bits (hex)   Check Bits (binary)  Spare Bit
             FFFFC000           1110000              1
             00003FFF           0100000              0

      If all of the memory is filled with only one ECC word and read
back and compared, then each data bit will have a continuous value.
In this case, some errors may go undetected due to capacitance on the
memory bus.  Therefore, the patterns will be chosen such that they
are a combination of the above ECC words.  The patterns selected to
set each bit to a 1 and a 0 are Patterns 1-3 following (Pattern 4
will be explained later).

      Pattern 1                 Pattern 2
  Interleave  ...