Browse Prior Art Database

Method for Testing the IPL ROS MEMORY TEST

IP.com Disclosure Number: IPCOM000102587D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 101K

Publishing Venue

IBM

Related People

Arimilli, LB: AUTHOR [+2]

Abstract

This article relates to testing the IPL ROS MEMORY TEST by using special hardware and software to strategically inject faults and check if these faults are detected and properly handled by the IPL ROS memory test.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for Testing the IPL ROS MEMORY TEST

       This article relates to testing the IPL ROS MEMORY TEST
by using special hardware and software to strategically inject faults
and check if these faults are detected and properly handled by the
IPL ROS memory test.

      The method presented here has two different applications.
First, as the code is being developed, each module of code which has
been written can be tested. Second, when the code is fully developed
and is passed on to system verification, the full code can be tested
as thoroughly as desired by simply adding more of the hardware and
software modules presented in this method and used in the test during
the debug stage of the code development.

      The method presented here is for testing the IPL ROS MEMORY
TEST for the IBM RISC System/6000*.  During this part of the IPL
sequence there are several tables and registers that are set up by
the IPL ROS code.  These tables and registers include:
 - Configuration registers that contain the size and base address of
each memory card.
     - Bit Steering (Sparing) control registers that control the bit
steering in the memory sub-system.
     - Bad page table that is used to indicate the 16 kbyte pages of
memory that are bad (contain bad bits after bit steering).

      This method of testing consists of hardware and software.  The
hardware is used to strategically inject faults on the memory bus at
specified addresses and bit positions.  The separate software is used
to check the IPL ROS MEMORY TEST's ability to detect the injected
faults and take appropriate action.  The test procedure is described
below.

      Test Procedure
 1. Install memory card(s) in slot(s) prescribed by the test.
 2. Set up the row/column addresses in the test hardware for the
desired address of the injected faults.
     3. Set up the bit position(s) in the test hardware for the
desired bit location(s) of the injected fault(s).
     4. Run the IPL ROS MEMORY TEST.
     5. Run the separate software which checks the necessary...