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System Debug Facility - A System Testing Computer Architecture for High-Speed Processing Systems

IP.com Disclosure Number: IPCOM000102589D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 6 page(s) / 246K

Publishing Venue

IBM

Related People

Davila, R: AUTHOR [+3]

Abstract

A system testing computer architecture called system debug facility (SDF) is described to support testing of special hardware and software needed for systems equipped with dual-bus architecture and advanced very large-scale integration (VLSI) technology.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 32% of the total text.

System Debug Facility - A System Testing Computer Architecture for High-Speed Processing Systems

       A system testing computer architecture called system
debug facility (SDF) is described to support testing of special
hardware and software needed for systems equipped with dual-bus
architecture and advanced very large-scale integration (VLSI)
technology.

      The SDF is a cycle control and acqusition system that controls
both the processor (or local bus), and I/O bus, such as the Micro
Channel*. The concept partitions the architecture between the local
bus and the I/O bus so as to allow extensions for different
processors and local architectures, as well as different I/O bus
architectures. The concept provides distinct advantages in that it:
(a) eliminates the need for a special processor to interface to the
local bus; (b) allows independent control over the local bus and I/O
bus; (c) provides real time trace buffer access of the local bus and
I/O bus; (d) has the ability to execute cycles without processor
intervention; and (e) provides separation of hardware to ease the
upgrading to different processors and I/O bus architectures.

      The term processor bus is referred to as the local bus and the
term Micro Channel is used when referring to the I/O bus.  This does
not imply that there is a limitation to the types of I/O bus support.

      The SDF departs from the traditional system architectures in
that it can control and monitor every signal that is on the local bus
as well as every signal on the Micro Channel.  It is designed to
capture and monitor all cycles executed by the central processing
unit (CPU) or by any device residing on the local bus.  It will
capture and monitor any bus master or direct memory access (DMA)
cycles executed on the Micro Channel bus at full operational speed
without affecting the real-time functionality of any cycle and are
monitored and controlled independently.  This allows the bus masters
and DMA operations to execute while the CPU is being held off and
vice versa.  Since the SDF hardware does not affect speed, processing
state, or real-time operations of the system, the data that is
captured and evaluated represents actual bus conditions on a
cycle-by-cycle basis.

      The SDF consists of two adapter circuit cards:  a Micro Channel
interface card (MCIC) residing in the Micro Channel of the system
under test (SUT) and a local bus interface card (LBIC) installed in
the processor of the SUT.  The LBIC is connected to the MCIC via
interface cables.  The SDF is controlled by an external monitor
system that passes data and control commands to and from the hardware
residing in the SUT. It is connected to the monitor system by means
of a cable.  The block diagram of Fig. 1 illustrates how the SDF is
connected.

      In order to provide independent control over the Micro Channel
and local bus, the logic is partitioned between the two adapter
cards.  The LBIC contains min...