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Test Patterns for 2-Way/4-Way Interleaved Memory Data Buses

IP.com Disclosure Number: IPCOM000102600D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 4 page(s) / 155K

Publishing Venue

IBM

Related People

Arimilli, LB: AUTHOR [+2]

Abstract

This article relates to testing the system memory for data errors during IPL by using data patterns that will be compatible with the both 2-way and 4-way interleaved memory cards.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Test Patterns for 2-Way/4-Way Interleaved Memory Data Buses

       This article relates to testing the system memory for
data errors during IPL by using data patterns that will be compatible
with the both 2-way and 4-way interleaved memory cards.

      There are two parts to a memory test:  an address test and a
data test.  The address test is responsible for testing for address
errors anywhere along the path from where they get generated to where
they reach the RAM chips. The data test will catch data errors in the
RAM chips or in the system wiring and buffering.  The data test uses
data patterns to test that each bit in memory can be toggled and the
data paths are good. Continued

      In the IBM RISC System/6000* it is possible to have 2-way or
4-way interleaved memory data buses (although the address and control
buses are 4-way interleaved).  Fig. 1 shows the 4 interleave bank
with 2-way interleaved data bus configuration.  Fig. 2 shows the 4
interleave bank with 4-way data bus configuration.
   Data Bits (in Hex)      Check Bits       Spare        Bit
                 AAAAAAAA             1001111             1
                 55555555             0011111             0

      Using the above ECC words, only two of the check bits will be
toggled.  Therefore, the following ECC words will be used in addition
to the above ECC words to toggle the rest of the check bits.  Only
one of the following two ECC words is needed to toggle the rest of
the check bits; however, both are used to toggle the maximum number
of bits of each transfer.
   Data Bits (in Hex)      Check Bits       Spare        Bit
                 FFFFC000             1110000             1
                 00003FFF             0100000             0

      Using these four ECC words, all of the data bits, check bits,
and spare bit will be toggled.  If all of the memory is filled with
one ECC word at a time and read back, then each bit will have a
continuous value.  Due to capacitance on the bus, some of the errors
may go undetected. Therefore, the test patterns will be a combination
of ECC words.

      The patterns in Fig. 3 were selected to toggle the data on the
two interleaved data buses shown in Fig. 1.  Patterns 1 and 2 were
chosen instead of alterna...