Browse Prior Art Database

Error Detection Method for Ram With Stuck Output Latches

IP.com Disclosure Number: IPCOM000102601D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 110K

Publishing Venue

IBM

Related People

Miracle, G: AUTHOR [+2]

Abstract

Parity-checked CMOS-2 porous, growable arrays can suffer a wordline failure, resulting in stuck array output latches and data integrity problems. For all of these problems, arrays that are sequentially accessed and wrap from the end to the beginning, the following general solution can be applied: define good even parity for all even-numbered array addresses, and good odd parity for all odd-numbered array addresses.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Error Detection Method for Ram With Stuck Output Latches

       Parity-checked CMOS-2 porous, growable arrays can suffer
a wordline failure, resulting in stuck array output latches and data
integrity problems.  For all of these problems, arrays that are
sequentially accessed and wrap from the end to the beginning, the
following general solution can be applied:  define good even parity
for all even-numbered array addresses, and good odd parity for all
odd-numbered array addresses.

      A data-integrity problem can occur in machines having customer
data that is buffered in certain imbedded CMOS-2 porous, growable RAM
arrays.  A wordline failure in a particular location can cause the
array output latches to remain unchanged when reading this location.
Thus, no error is detected when reading this bad location, because
the array output latches still contain the good-parity data left over
from reading some previous location that does not have a failure.  If
this array was being used by a channel as a data buffer, then the
damage done would depend whether a read or write operation was being
performed.  If a read operation were in progress, then this incorrect
data would be transferred into main storage, and the customer's
program could operate on the incorrect data.  If a write operation
was in progress, then this incorrect data would be written onto an
I/O device, contaminating the customer's data base. An undetected
data-integrity error is one of the worst possible problems in any
computer system.

      Many of the arrays that can have the wordline failure and can
contain data are always accessed sequentially through ascending
addresses, wrap from the maximum address to address zero if the
maximum address is reached, always start a new operation at location
zero, and always contain an even number of addresses.  Based on this
array usage, the following solution was adopted:
1.   Define alternating parity for sequentially-ascending
      addresses in these arrays as follows:
      -    Any even-address location will contain even-parity
           data, and
      -    Any odd-address location will contain odd-parity
           data.
      Generate the desired parity to be written based on the
      write address:  If the write address is even, then
      invert the parity bit for the data to be written into
      the array; if the write address is odd, then leave the
      parity bit unchanged.
      Check the parity read based on the read address:  If
      the read address is even, then invert the parity bit
      for the data read from the array; if the read address
      is odd, then leave the parity bit unchanged.
      If the array output latches do not alternate parity
      from even to odd to even...etc., as sequential
      locations are read from addresses 0 to 1 to 2...etc.,
 ...