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Circuit Scheme to Improve Chip Data Hold Time

IP.com Disclosure Number: IPCOM000102613D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 5 page(s) / 189K

Publishing Venue

IBM

Related People

Correale Jr, A: AUTHOR

Abstract

Chip data set-up and hold times are becoming increasingly more important as chip cycle times improve. Complex data input paths which involve multiplexing and multiple termination latches further complicate the designers' ability to provide optimal set-up-hold specifications. In addition, on-chip clock generating schemes can improve overall set-up time but generally result in hold-time degradation. Since hold time is an extremely important specification when one considers common I/O bus access, system performance can be improved with better hold times. The circuit scheme specified in this document can be utilized in conjunction with chip receivers, or other internal chip logic, to reduce the hold time without degrading the set-up time and thereby improve system performance.

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Circuit Scheme to Improve Chip Data Hold Time

       Chip data set-up and hold times are becoming increasingly
more important as chip cycle times improve.  Complex data input paths
which involve multiplexing and multiple termination latches further
complicate the designers' ability to provide optimal set-up-hold
specifications.  In addition, on-chip clock generating schemes can
improve overall set-up time but generally result in hold-time
degradation.  Since hold time is an extremely important specification
when one considers common I/O bus access, system performance can be
improved with better hold times. The circuit scheme specified in this
document can be utilized in conjunction with chip receivers, or other
internal chip logic, to reduce the hold time without degrading the
set-up time and thereby improve system performance.  Furthermore, if
internal timings associated with the paths after the received latched
data have latency, then improved overall set-up times are possible
without hold-time degradation.

      A typical chip external synchronous data interface is comprised
of receivers, some internal logic, and ultimately latches and
associated clocking to capture the data.  The receiver is connected
between the chip pin and the internal logic and is responsible for
levels conversion and redrive. The internal logic is connected
between the receiver output and the latch or latches to receive the
data.  In many designs, there are multiple latches which receive the
external data.  The delay paths associated with a common input to the
various latches can be vastly different.  Here lies one of the
problems of minimal set-up-hold time windows.  The set-up time must
be specified for the longest delay path whereas the hold time is
limited to the shortest delay path of the input.  Certainly, delay
path balancing can be utilized to reduce this, but the added
circuitry and area are difficult to justify.  In the single latch
scheme the disparity described above does not exist, but
nevertheless, the set-up-hold time window can be a problem if hold
time specifications of 0 ns or less are desirous.

      Fig. 1 illustrates the schematic representation of a typical
single-latch input path.  The input data is received by the input
receiver which performs the necessary levels translation, e.g., TTL
to CMOS, and redrives the signal. The latch data input is connected
to the output of receiver. The system clock is received on the chip
and directed to clock generation circuitry.  This clock generation
circuitry can be a single entity or a distributed local function.
The generator produces the multi-phase clocking scheme needed for the
design.  In this illustration, the 2-phase non-overlapping scheme is
used.  The phase 1 clock, hereafter referred to as the C1 clock, is
in phase with the system clock and out of phase with the phase 2
clock, hereafter referred to as the C2 clock.  The C1 clock is used
to gate the L1 latch, wherea...