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Browse Prior Art Database

Input/Output Computer Channel Utilization Control

IP.com Disclosure Number: IPCOM000102616D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 8 page(s) / 346K

Publishing Venue

IBM

Related People

Dixon, JD: AUTHOR [+7]

Abstract

A technique is described to provide a means of distributing the maximum sustained data transfer rate of an input/output (I/O) computer controller for extended periods of time so as to guarantee a constant percentage of bus cycles for the central processing unit (CPU).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 18% of the total text.

Input/Output Computer Channel Utilization Control

       A technique is described to provide a means of
distributing the maximum sustained data transfer rate of an
input/output (I/O) computer controller for extended periods of time
so as to guarantee a constant percentage of bus cycles for the
central processing unit (CPU).

      Typically, in multi-tasking computational environments, systems
will have peak periods of system bus utilization derived from high
throughput devices.  This results in non-buffered I/O devices,
serviced by the CPU, to be locked-out for periods of time so as to
cause operational over-runs or under-runs.  The concept described
herein provides a method of averaging the maximum sustained data
transfer rate of the high throughput buffered devices so that enough
system bus cycles will exist to prevent locked out problems.

      Fig. 1 shows a typical computer configuration whereby an I/O
controller and low function I/O devices utilize the same system bus
as the CPU and main memory.  Generally, when the CPU is in operation,
program execution will proceed and the I/O operations are blocked out
until the proper instructions are executed.  Alternatively, the
memory and system bus can be held by one of the I/O units for some
portion of a data move operation.  In this case, the CPU is denied
access to the main memory and cannot execute instructions until steps
are taken to halt or suspend that portion of the data move operation.
If data operations are suspended, serious performance problems can
exist or data is exposed to loss upon restart of a halted device
requiring an entire I/O operation to be repeated in order to
guarantee data integrity.

      One major area of impact of CPU lock-out is the ability to
support configurations, as shown in Fig. 1, such as low function I/O
devices or controllers.  A device is identified as a low function
type if the basic and on-going operation of that device requires
intervention by the CPU for associated I/O operations to proceed to
completion in a functionally correct manner.  For example, simple
asynchronous communications logic could require intervention by a CPU
service routine on each and every communications character.  If the
CPU is locked-out and cannot provide the required service in time,
then a data over-run/ under-run error will occur.

      In prior art, constricting limits were required in the
supported communications configurations.  It was necessary to reduce
some combinations of the data rate of each communications line and
the number of those communication lines supported.  This reduction
was based on a (peak demand) worst-case number of CPU instruction
cycles which were available in the time interval between characters
on one or more communication lines.  The concept described herein
provides a means to create the effect of redistributing, in time, the
pattern of I/O data moves so that peak levels of activity are
smoothed downward resul...