Browse Prior Art Database

Small Computer Systems Interface Identification Qualification During Selection/Deselection

IP.com Disclosure Number: IPCOM000102618D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Keener, DS: AUTHOR

Abstract

Described is a decoding method and hardware implementation for providing identification qualification during the selection/reselection process for small computer systems interface (SCSI) systems. The decoding method determines whether more than two lines of an eight-bit bus are active.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 82% of the total text.

Small Computer Systems Interface Identification Qualification During Selection/Deselection

       Described is a decoding method and hardware
implementation for providing identification qualification during the
selection/reselection process for small computer systems interface
(SCSI) systems.  The decoding method determines whether more than two
lines of an eight-bit bus are active.

      One of the requirements for SCSI systems is not to respond to a
selection or reselection phase if more than two bits of the SCSI data
bus are active (low) during either phase.  The two active bits
represent the user identification (ID) and the ID of the device
selecting or reselecting.  The device selecting or reselecting may or
may not place its ID bit on the bus and, therefore, the phase is
valid if one or two bits are active on the bus.

      Since there are many different combinations of eight bits with
only two low and eight situations with only one low, to decode these
combinations directly would be cumbersome and undesirable.  The
concept described herein provides a three-layer structure to count
the number of bits that are active.  Fig. 1 shows a block diagram of
the circuit structure.  The first layer consists of four identical
circuits with two data bits connected to the inputs.  The output of
each identical circuit indicates that zero, one or two bits are
active.  The second layer consists of two identical circuits whose
input connects to the output of the...