Browse Prior Art Database

LSSD Clock Multiplexer

IP.com Disclosure Number: IPCOM000102626D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Johnson, MA: AUTHOR

Abstract

The circuit described in this article allows two asynchronous clocks to independently control common LSSD latches and swaps control from one clock to the other without creating clocking problems inherent in multiplexing asynchronous clocks in an LSSD environment.

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This is the abbreviated version, containing approximately 52% of the total text.

LSSD Clock Multiplexer

       The circuit described in this article allows two
asynchronous clocks to independently control common LSSD latches and
swaps control from one clock to the other without creating clocking
problems inherent in multiplexing asynchronous clocks in an LSSD
environment.

      The problem of having to control one common set of logic with
multiple asynchronous clocks occurs frequently, especially in designs
that incorporate two separately clocked interfaces.  It is,
therefore, necessary to implement a circuit that allows the common
logic and its associated LSSD latches to avoid locking up in an
undesired state.

      The figure shows the LSSD Clock Multiplexer circuit. It
operates as follows:
o    The K+SG signal is from a primary I/O that is controlled by the
chip tester.  It is high during testing and low at all other times.
      o    The 'n' in the CLKn signals stand for 1, 2, or any number
that the designer chooses.  It is expressed in this way to indicate
that these clocks may be chosen at designer's discretion without any
impact on the performance of the circuit, since this clock is used
for LSSD test purposes only.
      o    The RESET signal must be active for at least two clock
periods of the slowest clock.  It should be synchronous to the CLKn
clocks.

      The CLK1->CLK2_PULSE is provided by CLK1 control logic to
signify that it wishes to surrender control to the CLK2 control
logic.  This signal is synchronous to the CLK1 control logic and is
one...