Browse Prior Art Database

Protection Logic for DRAM AC Failures

IP.com Disclosure Number: IPCOM000102649D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 87K

Publishing Venue

IBM

Related People

Borkenhagen, JM: AUTHOR [+3]

Abstract

A method to protect a CPU from DRAM AC failures on memory cards is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Protection Logic for DRAM AC Failures

       A method to protect a CPU from DRAM AC failures on memory
cards is disclosed.

      In order to protect a CPU from DRAM AC failures, data latches
were incorporated into a common memory interface to stabilize the
data coming from the DRAMs.  A necessary design constraint was that
the new design had to be functionally compatible with the existing
common memory interface in order to be completely transparent to the
system in which it was to operate.

      This constraint imposed the following groundrules on any
solution:
1.  Only the current set of asynchronous control signals defined to
the common memory interface could be used to generate the proper
latch clocking signal.
2.  All memory interface timings had to be maintained.
3.  The memory card signal I/O loading could not be increased.
4.  All normal and error recovery modes of card operation had to work
with the latches in the data path.

      The signal used to clock the data into the latch had to be an
existing control signal or a combination of existing signals defined
in the common memory interface specification.

      The latch clock signals had to function in a way to provide a
way to:
1.  Sense when data was valid from the memory array modules.
2.  Save data in the latch until the next memory access.
3.  Re-access the data saved in the latch for error recovery.

      No one control signal existed that met the necessary criteria
and combining signals with additional logic to produce a clock could
not be accomplished in the timing window required.  The problem was
solved by utilizing LSSD (Level-Sensitive Scan Design) latches in an
unconventional manner with existing asynchronous memory control
signals to achieve the design groundrules.

      The logic and timing diagrams shown in Fi...