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Browse Prior Art Database

Frame-Based Representation of the RISC State Machine

IP.com Disclosure Number: IPCOM000102660D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Barrett, KL: AUTHOR [+3]

Abstract

Disclosed is a method of representing the RISC state machine (registers, caches, memory) in a knowledge base.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Frame-Based Representation of the RISC State Machine

       Disclosed is a method of representing the RISC state
machine (registers, caches, memory) in a knowledge base.

      All Random-Access Storages are commonly referred to as RAL
(Random Access Location).  This class is subdivided into Registers,
Cache, Memory.  The hierarchy of these units is shown in the figure.

      The registers are further subdivided into Clock_regs,
FXU_pro_regs, FPU_pro_regs, Bra_pro_regs, P_int_regs, SCU_regs and
I/O_regs.  The P_int_regs (processor internal registers) is further
subdivided into DCU_regs and SCU_regs. Similarly, I/O_regs has
SLA_regs and IOCC_regs as its subclasses.  Under SLA_regs, there are
SLA0_regs, SLA1_regs, SLA2_regs, and SLA3_regs since there are four
SLA units in the RISC System/6000*.

      The cache unit has two subclasses: ICU_array and DCU_array.
The CURVAL_TC slot of RAL is the plate-holder that holds the content
of that storage element (registers, cache, memory).

      The registers are represented as units with a
field-subfield-bit structure.  The memory and cache are represented
as sets of hash tables.

      These storage elements are used to store values as they are
computed, changed, while the test case is generated by IVGEN.
*  Trademark of IBM Corp.