Browse Prior Art Database

Self-Aligned Layer for Reduction of Soft Errors

IP.com Disclosure Number: IPCOM000102680D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Joshi, ML: AUTHOR [+4]

Abstract

A P-type buried layer is self-aligned to a sub-collector mask for soft error rate (SER) reduction in a bipolar complementary metal oxide silicon (BICMOS) process. This medium doped layer beneath N+ diffusions of static random access memory (SRAM) cells prevents loss of information due to charge generation by alpha particles.

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Self-Aligned Layer for Reduction of Soft Errors

       A P-type buried layer is self-aligned to a sub-collector
mask for soft error rate (SER) reduction in a bipolar complementary
metal oxide silicon (BICMOS) process.  This medium doped layer
beneath N+ diffusions of static random access memory (SRAM) cells
prevents loss of information due to charge generation by alpha
particles.

      The cross-section shown in Fig. 1 is created by growing oxide
10 over the whole surface of silicon wafer 12, implanting oxide 10
with arsenic (As), depositing nitride 14 over the whole wafer,
generating photoresist mask 16, anisotropically etching away all
exposed oxide 10 and nitride 14, ion implanting boron (B) in regions
18, and then isotropically etching nitride 14 and oxide 10 to
undercut photoresist 16 as shown.

      Photoresist 16 is then removed, arsenic is driven from oxide 10
to form doped region 20 shown in Fig. 2.  Recessed oxide 22 is then
formed.

      Nitride 14 is removed and oxide layers 10 and 22 are removed to
leave the cross-section shown in Fig. 3.  Having thus formed
subcollector doped region 20 and self-aligned, P-type layer 18,
standard processing is used to complete BICMOS devices and circuits.
Diffusions 18 are used to minimize the impact of charge generated by
ionizing radiation penetrating the silicon.  SER is thereby
significantly reduced.