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Browse Prior Art Database

Program Controlled Micro Channel Bus Cycle Extension

IP.com Disclosure Number: IPCOM000102681D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 121K

Publishing Venue

IBM

Related People

Chisholm, DR: AUTHOR [+2]

Abstract

A technique is described whereby computer systems which utilize the Micro Channel* (MC) are provided program controlled bus cycle extension capability so as to compensate for attached slave devices with marginal timings.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Program Controlled Micro Channel Bus Cycle Extension

       A technique is described whereby computer systems which
utilize the Micro Channel* (MC) are provided program controlled bus
cycle extension capability so as to compensate for attached slave
devices with marginal timings.

      During MC bus operations certain attached slave devices, such
as MC attachments which respond to MC control signals, may have
marginal timings that may affect the application that is being run by
the master device.  The concept described herein provides a
program-controlled bus cycle extension capability that effectively
lengthens default bus cycle timings so that the marginal slave
devices will not affect system operation, primarily in streaming and
non-streaming data cycles.

      Fig. 1 shows the timing for a typical non-streaming default
cycle.  The architecture is such that in MC bus operation, channel
ready (CHRDY) must be returned within 60 ns from when valid MC
addresses are present. This is shown as the time between A and B.  If
the slave device were to take slightly longer, the bus master may
miss the indication that the slave device was not ready and will
execute a default cycle instead of a synchronous extended or
asynchronous extended cycle.  This could cause incorrect data being
sent or received from the slave device being addressed.  If the slave
supports a default cycle, but takes slightly longer than the
architected time to provide valid data (the time C to D), this
technique can be used to prevent invalid data from being received by
the bus master.

      To correct this problem, a certain time period is inserted by
the bus master to allow for a delayed CHRDY low signal.  MC bus
master chip set (BMCS) inserts 100 ns (if programmed) before it even
begins checking for CHRDY.  If, at the end of that time, CHRDY is
detected as being high, the cycle continues as if nothing was
changed.  Therefore, a default cycle is extended from 200 ns to 300
ns.  If, at the end of that time, CHRDY is detected as being low, the
cycle continues as an asynchronous extended cycle.  This allows time
to check for a slow CHRDY and late data from a...