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Process for Simultaneously Forming Poly/EPI Silicon Filled Deep And Shallow Isolation Trenches Having a CVD Oxide Cap

IP.com Disclosure Number: IPCOM000102683D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 5 page(s) / 154K

Publishing Venue

IBM

Related People

Burger, RE: AUTHOR [+5]

Abstract

Both deep (~4.0 - 6.0 um) and shallow (~0.5 - 1.0 um) isolation trenches are necessary to increase density and to reduce capacitance in the fabrication of VLSI semiconductor substrates (*). This article describes a process for forming deep (polysilicon filled and oxide-capped) trenches for device isolation and shallow (oxide-filled) trenches for base to subcollector reachthrough diffusion isolation. This process involves simultaneously recessing the polysilicon trench fill, forming shallow trenches in silicon (by etching), depositing CVD (chemical vapor deposited) oxide, and polishing the oxide to provide an oxide cap for the deep trench and oxide fill for the shallow trench.

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Process for Simultaneously Forming Poly/EPI Silicon Filled Deep And Shallow Isolation Trenches Having a CVD Oxide Cap

       Both deep (~4.0 - 6.0 um) and shallow (~0.5 - 1.0 um)
isolation trenches are necessary to increase density and to reduce
capacitance in the fabrication of VLSI semiconductor substrates (*).
This article describes a process for forming deep (polysilicon filled
and oxide-capped) trenches for device isolation and shallow
(oxide-filled) trenches for base to subcollector reachthrough
diffusion isolation.  This process involves simultaneously recessing
the polysilicon trench fill, forming shallow trenches in silicon (by
etching), depositing CVD (chemical vapor deposited) oxide, and
polishing the oxide to provide an oxide cap for the deep trench and
oxide fill for the shallow trench.

      The formation of an "oxide plug" over a partially filled
silicon trench is known.  In brief, a timed RIE (reactive ion etch)
etching (precise control of silicon recess) of a silicon or
polysilicon (poly) filled trench is performed and planarization by
chemical-mechanical polishing.  The "oxide plug" itself is fabricated
by CVD SiO2 deposition processes, followed again through
planarization by chemical-mechanical polishing.  Vertical "bird's
beaking", and other defects formerly encountered with the use of ROI
(recessed oxide isolation) etching during "oxide plug" formation, are
avoided by not using a thermal oxidation process.  This "oxide plug"
PST (polysilicon trench) isolation technology is extended, allowing
formation of the shallow trench at the same time as the silicon
trench recess process (see Figs.  1 through 6), and the silicon level
in the recessed PST trench is approximately the same as the bottom
silicon surface of the shallow trench.

      Fig. 1 illustrates a CVD SiO2 layer 1 deposition on planarized
silicon filled trenches 2 and 3.  The SiO2 is ~3000 angstroms thick.
Also shown are a polishing stop layer of 1000 to 1500 angstroms of
Si3N4 4 and a 500 - 3000 angstrom layer of thermal SiO2 5.

      Fig. 2 shows the previous structure after photo delineation and
timed RIE etching o...