Browse Prior Art Database

Automatic Method for Registration And Stacking of Laminates

IP.com Disclosure Number: IPCOM000102691D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 5 page(s) / 232K

Publishing Venue

IBM

Related People

Hollis Jr, RL: AUTHOR

Abstract

This article discusses a method for automatically registering and stacking thin laminates such as those used in printed circuit board manufacturing.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 27% of the total text.

Automatic Method for Registration And Stacking of Laminates

       This article discusses a method for automatically
registering and stacking thin laminates such as those used in printed
circuit board manufacturing.

      To create high-density wiring boards, it is necessary to make
many individual wiring layers on thin sublaminates. The exact
technology required varies from product to product and is not
relevant here.  Each layer is fabricated using photolithographic
means to an accuracy sufficient for the product ground rule
requirements and for sufficient overlap of vertical connections
(vias) when laminated together into a board.  It is standard practice
to include fiducial markings in the corners of each sublaminate to
aid in the alignment process.  These fiducials are created in the
same step as the circuitry artwork and are, therefore, very well
registered to the wiring features.

      In the usual procedure for assembling a wiring board, accurate
holes are punched in each layer, referenced from the fiducial marks.
The layers are then stacked on close-fitting pins to insure good
layerto-layer registration.

      As product artwork dimensions decrease, the likelihood of
layer-to-layer misregistration increases.  It is not clear now that
the traditional punched-hole-and-pin method will continue to give the
required degree of accuracy.  This method places stringent demands on
machining methods and material properties.  For example, if several
pins are used around the periphery, then allowance must be made for
variation in their absolute positions.  On the other hand, if they
are used only along one edge, then the degree of via alignment will
be high near that edge, but lower away from the edge.  Some
tolerances exist on both hole and pin diameters; hence clearance must
be provided, limiting the achievable registration accuracy.

      Further, there may be difficulty in maintaining alignments by
this method during the pressing and baking cycle necessary to fuse
the sublaminates together to make a functional board.

      Finally, there is the problem of handling thin sublaminates and
slipping them onto the alignment pins without damaging them.  Even
with tapered pins, this can be a severe problem, and is at best a
very tedious job which is difficult to automate.

      The method proposed here offers a solution to the manufacturing
problems given above:  a general-purpose robot equipped with an x, y,
Rz fine motion device, such as the IBM Production Fine Positioner, is
used with fiducial sensors to automatically register and stack the
sublaminates.

      The figure is a schematic sketch of the automatic
stacker/aligner system.  A suggested sequence of operations follows:
1.  To begin with, sublaminate layers L1, L2, L3, etc., are loose
ly stacked in bins.
2.  The robot carrying the fine positioner comes over to the first
      layer, L1, and picks it up using a vacuum suction
    ...