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Confirmed Prefetching Using a Modified Decode History Table

IP.com Disclosure Number: IPCOM000102711D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Cocke, J: AUTHOR [+6]

Abstract

Let us consider a processor with fixed instruction size (4 bytes), a conditional branch relative instruction, and a decode history table (DHT) maintained for these instructions. Let us further assume that the cache and the memory are addressed with real address bits while the DHT and processor use logical or virtual addresses. The prefetching mechanism that is about to be described will allow a modified version of the DHT to confirm the prefetching decisions that are made by a snooping device that monitors the cache-memory bus during the miss.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Confirmed Prefetching Using a Modified Decode History Table

       Let us consider a processor with fixed instruction size
(4 bytes), a conditional branch relative instruction, and a decode
history table (DHT) maintained for these instructions. Let us further
assume that the cache and the memory are addressed with real address
bits while the DHT and processor use logical or virtual addresses.
The prefetching mechanism that is about to be described will allow a
modified version of the DHT to confirm the prefetching decisions that
are made by a snooping device that monitors the cache-memory bus
during the miss.

      To distinguish the DHT which is used by the processor to
predict branches and the DHT that is used by the prefetching
mechanism, the former will be called simply the DHT and the latter
DHT_PM.  When the processor resolves a branch relative instruction it
will access with DHT and set the branch action both the DHT and the
DHT_PM based on the virtual address on the branch instruction.
Although the processor is the sole means by which the DHT is updated,
the DHT_PM is also updated by the CONFIRMATION BUFFER that is
associated with the prefetching mechanism.

      The basic action during the transfer of a line from the memory
to the cache is for the bus to be monitored (see U.S. Patent
4,437,149) for a BRANCH RELATIVE instruction. As the line missing is
within a particular page, the portion of the address needed to
compute the virtual address within the DHT_PM is made available based
on the logical address that caused the miss. The miss to a real
address results from translation of this virtual address though a
DLAT like mechanism. By accessing the DHT_PM to determine if the
action of any BRANCH RELATIVE instruction is predicted as taken, the
snooping mechanism can then compute the target of the TAKEN branch
and determine if it is within the current cache line. If it is not,
the virtual address of this line is sent to the DLAT to initiate the
prefetch of the next...