Browse Prior Art Database

Monitoring of Computer Systems Input/Output Bus Functions

IP.com Disclosure Number: IPCOM000102713D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 3 page(s) / 126K

Publishing Venue

IBM

Related People

Bustamante, C: AUTHOR [+5]

Abstract

Described is an apparatus and method for data capture for monitoring, collecting and formatting the input/output (I/O) bus activity of computer systems. The facility is designed to capture execution flow of the I/O bus of computers and can be used for tracing program execution flow (to the extent of disassembling instruction fetch cycles visible on the I/O bus), and for capturing any activity on the I/O adapter bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Monitoring of Computer Systems Input/Output Bus Functions

       Described is an apparatus and method for data capture for
monitoring, collecting and formatting the input/output (I/O) bus
activity of computer systems.  The facility is designed to capture
execution flow of the I/O bus of computers and can be used for
tracing program execution flow (to the extent of disassembling
instruction fetch cycles visible on the I/O bus), and for capturing
any activity on the I/O adapter bus.

      The facility, operating under program control, selectively
captures, formats and presents I/O bus information for analysis.  It
can be used to trace software programs, direct memory access (DMA)
functions, I/O operations, interrupts, etc.  Fig. 1 shows the basic
overview of the facility which consists of three basic units:  a) I/O
bus adapter card 10, which is installed in the system being analyzed;
b) parallel port cable 11; and c) control system 12, which includes a
bidirectional parallel port.  The facility communicates through I/O
bus adapter card 10 to the bidirectional parallel port of control
system 12 under control of the software of control system 12 and a
microprocessor on I/O bus adapter card 10.

      A block diagram of the control program process is shown in Fig.
2.  In normal operation, the facility operates synchronously with the
I/O adapter bus of the computer system being analyzed.  Each class of
information on the bus is stored in temporary latches at the time in
the bus cycle when the class of information is known to be valid.
Near the end of the bus cycle, the temporary latches are written to a
static random access memory (SRAM) which is capable of storing the
information captured.  Three classes of information are captured from
the I/O adapter bus:  Status, Data, and Address.  An additional class
of information, called Clock, is generated internally by the card and
stored in the SRAM along with the information captured from the I/O
bus. Clock provides a method of time-stamping each captured cycle by
recording the duration of the current cycle and the elapsed time
since the previous captured cycle.

      The facility includes a number of programmable data probes,
which the user can attach to signal sources in the computer system
under analysis.  The information on the probes is recorded in the
SRAM along with the information described above.  A handshake
protocol is used to communicate between control system 12 and I/O
adapter card 10 and responds to five commands:  reset; initialize
SRAM; set configuration mode; set capture mode; and set transfer
mode.  After each of these command...