Browse Prior Art Database

Procedure for Ordering Global Nets Crossing Macro Boundaries

IP.com Disclosure Number: IPCOM000102718D
Original Publication Date: 1990-Dec-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 6 page(s) / 209K

Publishing Venue

IBM

Related People

Hauge, PS: AUTHOR [+2]

Abstract

The herein-disclosed procedure relates in general to automated VLSI chip physical design and silicon compilers. For the method of physical design in which chips are formed by abutting macros which contain both native and foreign global wires, the sequential order in which the global nets are placed along intermacro edges is important. This problem is related to ordering nets along the boundaries of the regions dedicated to wiring found in gate array, standard cell or custom chip layouts, in which circuit regions are not contiguous, but the present problem is more general and must meet a different set of requirements. This procedure comprises a simple and computationally fast constructive way for determining desirable orderings for the sets of nets associated with each intermacro edge on a chip.

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Procedure for Ordering Global Nets Crossing Macro Boundaries

       The herein-disclosed procedure relates in general to
automated VLSI chip physical design and silicon compilers. For the
method of physical design in which chips are formed by abutting
macros which contain both native and foreign global wires, the
sequential order in which the global nets are placed along intermacro
edges is important.  This problem is related to ordering nets along
the boundaries of the regions dedicated to wiring found in gate
array, standard cell or custom chip layouts, in which circuit regions
are not contiguous, but the present problem is more general and must
meet a different set of requirements.  This procedure comprises a
simple and computationally fast constructive way for determining
desirable orderings for the sets of nets associated with each
intermacro edge on a chip.

      A method of chip physical design has been previously disclosed
in (*) in which both foreign and native global nets (nets which
connect two or more macros) are allowed to pass through macros.
Here, "native" refers to global nets which connect to a particular
macro; "foreign" refers to global nets which pass through the macro
without making an electrical connection.  This method takes advantage
of macro porosity to reduce the amount of chip area required for
intermacro wiring.

      After macro locations and shapes have been determined, for
example, by a floorplanning program, global wiring is done.  A
routing is found for each global net.  Each route is a path
(specified by a sequence of macros) which crosses a string of
intermacro edges.  Along any intermacro edge, the global router does
not order the nets.  This disclosure addresses the problem of
ordering nets along macro boundaries.  This is an important problem
because a poor net ordering adversely affects chip wirability.

      Used as a region for global wires, a macro differs from a
dedicated wiring area in several ways.  A macro's area is determined
primarily by the number of devices it contains, and hence is
insensitive to the details of the path a wire takes in going through
it.  Fig. 1 graphically illustrates a typical path of a foreign
global net through a macro.  As Fig. 1 indicates, a global wire is
not likely to follow a straight path through a macro; rather, a path
may switch tracks several times in order to avoid device blockages
and tracks occupied by other wires.  The conditions for a good net
ordering (and subsequent track assignment) are thus somewhat relaxed
compared to those for using clear wiring channels, in that entrance
and exit tracks need not be matched, and inter-wiring-plane vias do
not incur an explicit area penalty.

      When macros are used for global wiring, the main consideration
for net order along intermacro boundaries is wire length.  For a
given net ordering there is a minimum path length for each net
traversing a given macro.  The goal of net orde...