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Browse Prior Art Database

Dynamic Command Execution

IP.com Disclosure Number: IPCOM000102723D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 55K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+3]

Abstract

The processor in a computer system typically issues PIO (Programmed I/O) operations to access I/O data. High performance computer systems will typically have an isolated processor complex to achieve fast cycle times. When the processor issues a PIO to an IOCC (I/O Channel Controller), significant latency may exist between the two subsystems. Due to this structure in high performance computer systems, special PIO operations, called PIO Commands, are issued by the processor to allow the IOCC to perform either multiple PIOs, or unique IOCC functions. One such system contains an IOCC which improves processor PIO performance, and I/O DMA (Direct Memory Access) performance by allowing dynamic command execution. Also, dynamic command execution allows real-time commands to achieve optimal timing accuracy.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 67% of the total text.

Dynamic Command Execution

      The processor in a computer system typically issues PIO
(Programmed I/O) operations to access I/O data.  High performance
computer systems will typically have an isolated processor complex to
achieve fast cycle times. When the processor issues a PIO to an IOCC
(I/O Channel Controller), significant latency may exist between the
two subsystems. Due to this structure in high performance computer
systems, special PIO operations, called PIO Commands, are issued by
the processor to allow the IOCC to perform either multiple PIOs, or
unique IOCC functions.  One such system contains an IOCC which
improves processor PIO performance, and I/O DMA (Direct Memory
Access) performance by allowing dynamic command execution. Also,
dynamic command execution allows real-time commands to achieve
optimal timing accuracy.

      The IOCC is architected to receive and execute PIO operations
from the processor.  Certain PIO operations, however, are decoded by
the IOCC, as internal IOCC commands. However, to minimize any special
hardware, all of these commands were architected to appear as an I/O
operation on the I/O bus.  This means that to execute any command,
one must first own the I/O bus (as is the case for normal PIO
operations).  To own the I/O bus, one might have to preempt a DMA
transfer on the bus.  Certain commands, however, have no need to
actually own the I/O bus to perform the execution of the command.
During these commands, some extra logi...