Browse Prior Art Database

Overlapped PIO Operations

IP.com Disclosure Number: IPCOM000102725D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 47K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+4]

Abstract

The IOCC (I/O Channel Controller) architecture of computer systems typically do not allow processor PIO (Programmed I/O) execution with DMA (Direct Memory Access) transfers to the same I/O bus. Disclosed is a means by which the one system's IOCC improved the processor's PIO performance by overlapping PIO execution with DMA transfers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 81% of the total text.

Overlapped PIO Operations

      The IOCC (I/O Channel Controller) architecture of computer
systems typically do not allow processor PIO (Programmed I/O)
execution with DMA (Direct Memory Access) transfers to the same I/O
bus.  Disclosed is a means by which the one system's IOCC improved
the processor's PIO performance by overlapping PIO execution with DMA
transfers.

      The IOCC has the capability of accepting a LOAD/STORE operation
from the processor while a DMA transfer is in progress on the I/O
bus.  This allows the IOCC to preempt the DMA device on the bus and
start the PIO cycles on the I/O bus as soon as possible (since the
latency between the receiving of the PIO from the processor, and the
IOCC, was overlapped with the DMA transfers).  Also, since the IOCC
has accepted the LOAD/STORE operation, the processor can continue
executing instructions after a STORE operation, or after a LOAD
operation in which the LOAD data is not required by the processor
(until some instructions later). Typically, most processors on an I/O
bus require ownership of the bus before they can issue a PIO
operation.  The architecture of the IOCC allows the IOCC to accept
all PIO operations (even if a DMA device currently owns the I/O bus),
thus freeing the processor from having to wait on the I/O bus.  This
allows the processor to greatly improve PIO performance.  Note that
certain processors wait on every LOAD/STORE operation to complete
before continuing instruction execution...