Browse Prior Art Database

Cache Coherency Data Alignment

IP.com Disclosure Number: IPCOM000102727D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 64K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+4]

Abstract

High performance computer systems will typically utilize cache memories to hold copies of a portion of the main system memory for faster access. When data is moved from the main memory to be used in the cache memory, the cache memory becomes the current memory image. Multiple processes can share the same main system memory and each may have their own cache, which creates a cache coherency exposure. Cache coherency problems arise when a second process accesses an area of main memory that has previously been copied into another cache to be modified. Cache memory management is a complex task that all high performance computer systems must handle.

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Cache Coherency Data Alignment

      High performance computer systems will typically utilize cache
memories to hold copies of a portion of the main system memory for
faster access. When data is moved from the main memory to be used in
the cache memory, the cache memory becomes the current memory image.
Multiple processes can share the same main system memory and each may
have their own cache, which creates a cache coherency exposure.
Cache coherency problems arise when a second process accesses an area
of main memory that has previously been copied into another cache to
be modified.  Cache memory management is a complex task that all high
performance computer systems must handle.

      One such system solved the cache coherency exposure with a
special operation called PIO (Programmed I/O) to System Memory.
Caches exit for both the processor and I/O interfaces to system
memory.  The I/O interface can be either PIO or DMA (Direct Memory
Access).  When the program allocates main memory space to an I/O
device operating in DMA mode, the program marks that area as being
exposed to a modification by an I/O device.  Any subsequent direct
access to this main memory range is subject to error, and instead the
processor accesses this address range indirectly through the IOCC
(I/O Channel Controller) with the PIO to System memory function.

      The IOCC contains separate PIO and DMA data buffers. The DMA
data buffers implement the I/O cache and PIO data buffers tempo...