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Process for Anisotropic High Etch Rate Ratio of Polysilicon To Silicon Dioxide

IP.com Disclosure Number: IPCOM000102733D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 34K

Publishing Venue

IBM

Related People

Cox, RD: AUTHOR [+3]

Abstract

High etch rate ratio (ERR) of polysilicon to silicon dioxide (SiO2) in a chlorine-based reactive ion etch (RIE) process can be achieved by increasing system pressure, oxygen (O2) flow or decreasing DC bias. By using decreased substrate temperature in the high ERR process, isotropic etching and undercutting are avoided.

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Process for Anisotropic High Etch Rate Ratio of Polysilicon To Silicon Dioxide

      High etch rate ratio (ERR) of polysilicon to silicon dioxide
(SiO2) in a chlorine-based reactive ion etch (RIE) process can be
achieved by increasing system pressure, oxygen (O2) flow or
decreasing DC bias. By using decreased substrate temperature in the
high ERR process, isotropic etching and undercutting are avoided.

      As dimensions of features being etched in polysilicon and
thickness of underlying SiO2 are reduced, a process window of
acceptable ERR and undercut becomes very narrow with consequent yield
instability in the chlorine-based RIE process.  It is known that
increased system pressure or an increase in oxygen flow or a
decreased DC substrate bias improves the ERR of polysilicon to SiO2 .
However, it is found that unacceptable polysilicon undercut is the
result of these changes to improve ERR when a normal substrate
temperature of about 45 degrees Celsius is maintained.  By reducing
substrate temperature to approximately zero degrees Celsius and
decreasing DC substrate bias voltage by about 15%, improved ERR is
achieved with no measureable undercutting or loss of etching
anisotropy.

      Disclosed anonymously.