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MOSFET On-Resistance Compensating Resistor

IP.com Disclosure Number: IPCOM000102752D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 49K

Publishing Venue

IBM

Related People

Gregor, RP: AUTHOR

Abstract

Disclosed is a polysilicon resistor design for integrated circuits which compensates for MOSFET on-resistance variations caused by process variations of the polysilicon gate channel length.

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This is the abbreviated version, containing approximately 85% of the total text.

MOSFET On-Resistance Compensating Resistor

      Disclosed is a polysilicon resistor design for integrated
circuits which compensates for MOSFET on-resistance variations caused
by process variations of the polysilicon gate channel length.

      A large part of the on-resistance variations of a MOSFET are
caused by variations in the polysilicon gate due to photo- lithograpy
and etching variations.  To compensate for the on-resistance
variations caused by the above-mentioned effects, a polysilicon
compensating resistor is placed in series with either the drain or
source of the FET to be compensated.  The resistor is designed by
using multiple parallel fingers of minimum width polysilicon, see
figure.

      Since the resistor is formed in the same process steps as the
FET polysilicon gate, the width of the polysilicon fingers of the
resistor will track the FET gate definition. As the polysilicon lines
become narrower, the FET on-resistance decreases and the resistance
of the compensating resistor increases, keeping the total series
resistance constant.  In contrast, previous approaches which put a
process insensitive resistor in series with the FET decrease the
magnitude of the on-resistance excursions, but cannot actually
compensate for them.  The ratio of the width of the polysilicon
resistor fingers to the FET gate line definition, and the ratio of
the total resistance of the compensating resistor to the FET
on-resistance, can be adjusted to either exactly...