Browse Prior Art Database

Address Instruction Pretranslation Buffer

IP.com Disclosure Number: IPCOM000102763D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 37K

Publishing Venue

IBM

Related People

Hattersley, J: AUTHOR

Abstract

In normal operation a vector instruction would calculate the first address of an instruction after it had completed the last instruction. This would cause gaps in the generation of addresses. The gap would be several cycles if the new translation was in the DLAT and 80 or more if the translation was not in the DLAT. This invention removes the gaps between instructions.

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Address Instruction Pretranslation Buffer

      In normal operation a vector instruction would calculate the
first address of an instruction after it had completed the last
instruction.  This would cause gaps in the generation of addresses.
The gap would be several cycles if the new translation was in the
DLAT and 80 or more if the translation was not in the DLAT.  This
invention removes the gaps between instructions.

      The addressing vector instructions are prefetched and put in a
buffer waiting for processing.  While the instruction waits for an
available address generator, the first address of the instruction is
generated and sent to the DLAT for translation.  The DLAT translates
the address on a low priority basis and puts the absolute address in
the buffer.  The starting address is now available when it is time
for this instruction to begin.  The second address is calculated in
the same cycle the first is issued so we now have a seamless
operation.

      This will avoid having gaps in address generation and memory
data transfers between instructions.

      Disclosed anonymously.