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Double Error Correction With Two Level ECC

IP.com Disclosure Number: IPCOM000102771D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 7K

Publishing Venue

IBM

Related People

Bossen, DC: AUTHOR [+2]

Abstract

Disclosed is a scheme to correct double bit errors at the system level for computer memory systems that employ both chip level and system level error correcting codes (ECC).

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Double Error Correction With Two Level ECC

Disclosed is a scheme to correct double bit errors at the system level for computer memory systems that employ both chip level and system level error correcting codes (ECC).

Let ECC0 be the chip level ECC and ECC1 be the system level ECC, and both codes are capable of correcting all single errors and detecting all double errors in a code word. Without ECC0, a special algorithm known as the double complement (for complement/recomplement) algorithm is used to correct and recover the data whenever there is a double error in a code word, provided that at least one of the double errors is a reproducible hard error. In the two level ECC environment, the double complement algorithm is not able to correct double hard errors at the system level because double hard errors are masked by the chip level ECC.

The disclosed scheme for double error correction requires that each array chip provide an input/output pin to indicate an uncorrectable error (UE) for ECC0. Let U be a binary vector that contains ones in positions of the chips that have turned on UE signals. As shown in the flow chart, the scheme is to correct errors as long as they are correctable by ECC1. When the errors are uncorrectable by ECC1, the number of ones in the UE indicator U is counted. If the number is exactly equal to two, the word Wm is set to be the Exclusive OR of the word W read from the memory and the chip UE indicator U. Then ECC1 recalculates the syndrome...