Browse Prior Art Database

Enhanced Overlap in Multiple E-Unit Processors

IP.com Disclosure Number: IPCOM000102785D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 43K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

Overlap between multiple execution units (E-units) can be enhanced by proper allocation of the operand activity. Comparison of the performance of multiple E-units and their effect on the E-unit busy time illustrates that there is little overlap between E-units if only one instruction is decoded per cycle. The basic idea of the present invention is to allow single cycle instructions to preempt the bus from multi-cycle operations which are already in progress.

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This is the abbreviated version, containing approximately 88% of the total text.

Enhanced Overlap in Multiple E-Unit Processors

      Overlap between multiple execution units (E-units) can be
enhanced by proper allocation of the operand activity. Comparison of
the performance of multiple E-units and their effect on the E-unit
busy time illustrates that there is little overlap between E-units if
only one instruction is decoded per cycle.  The basic idea of the
present invention is to allow single cycle instructions to preempt
the bus from multi-cycle operations which are already in progress.

      There are four things to be considered in deciding whether or
not to preempt a conceptually earlier instruction in favor of a later
one:
1.  E-unit queue size.
2.  Blocking instruction.
3.  Number of blocked non-memory accessing instructions.
 *  Such instructions will be referred to as RR instructions no
matter what their format.
4.  Level (or degree) of conditionality (LOC) associated with queued
instructions.

      Preempting the bus is useful only to the extent that it allows
blocked RR instructions to execute in parallel with instructions that
utilize the cache bus.  The algorithm is to preempt the cache bus for
all memory access requests from other queues at the same LOC as the
multi-cycle instruction using the bus whether or not there are
blocked RR instructions at that LOC in the queue.  The bus is
preempted for instructions at the next LOC only in the presence of
blocked RR instructions at that level.  A branch is considered to...