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A 5v CMOS Circuit Using Low-Voltage CMOS Devices

IP.com Disclosure Number: IPCOM000102790D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 33K

Publishing Venue

IBM

Related People

Chang, WH: AUTHOR

Abstract

Disclosed is a CMOS circuit which uses low-voltage devices but operates at a higher external power supply voltage. A standard 2-input NAND circuit is shown in Fig. 1. The new circuit is shown in Fig. 2. Each of the pFET devices in Fig. 1 is replaced in Fig. 2 by a series combination of the same pFET device, whose gate voltage is DC biased at REFP, is inserted in series with the nFET devices in Fig. 1. The Reference voltages REFN and REFP are generated elsewhere. Depending on the output level required, one of the above additional devices may be omitted. In operation, the standard portion of the NAND circuit operates on power supply voltage between REFN-Vtn and REFP+Vtp, where Vtn and Vtp are the threshold voltages of the nFET and pFET devices.

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A 5v CMOS Circuit Using Low-Voltage CMOS Devices

      Disclosed is a CMOS circuit which uses low-voltage devices but
operates at a higher external power supply voltage.  A standard
2-input NAND circuit is shown in Fig. 1.  The new circuit is shown in
Fig. 2.  Each of the pFET devices in Fig. 1 is replaced in Fig. 2
by a series combination of the same pFET device, whose gate voltage
is DC biased at REFP, is inserted in series with the nFET devices in
Fig. 1. The Reference voltages REFN and REFP are generated elsewhere.
Depending on the output level required, one of the above additional
devices may be omitted.  In operation, the standard portion of the
NAND circuit operates on power supply voltage between REFN-Vtn and
REFP+Vtp, where Vtn and Vtp are the threshold voltages of the nFET
and pFET devices. The advantage of such a circuit is that the devices
see a reduction in power supply voltage so that higher external power
supply voltage may be used.

      Disclosed anonymously.