Browse Prior Art Database

Single Clocked Syncing Data Buffer Ram

IP.com Disclosure Number: IPCOM000102794D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 34K

Publishing Venue

IBM

Related People

Peterson, MJ: AUTHOR [+4]

Abstract

Disclosed is a method of transferring electronic data across asynchronous logic boundaries through a RAM.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Single Clocked Syncing Data Buffer Ram

      Disclosed is a method of transferring electronic data across
asynchronous logic boundaries through a RAM.

      This transfer uses the unidirectional sync buffer of another
disclosure (see UniDirectional Synchronization Buffers published in
Research Disclosure, #30754, November 1989) to implement a
Bi-Directional Data Buffer.  In figure 1, the unidirectional sync
buffers convert all data to and from the RAM to the processor clock.

      The main feature of this design is that the RAM is read and
written by logic that all runs off the same clock.  This provides all
of the following benefits:
- Fewer circuits run on the fastest clock, reducing cross       talk,
radiation and power consumption.
- No clock switching is required for LSSD testing or self test, thus
allowing these tests 100% access to the functional paths.
      - All of the RAM time critical control is generated by a single
clock, thus avoiding further complications from clock switching.

      Disclosed anonymously.