Browse Prior Art Database

Variable Response, On Chip, Low Voltage Supply

IP.com Disclosure Number: IPCOM000102798D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 47K

Publishing Venue

IBM

Related People

Furst, RC: AUTHOR [+2]

Abstract

An on-chip three-volt power supply for the memory array portion of a five-volt circuit design uses low standby power and has a fast, accurate response to high current demands. A smooth transition from a high current state back to high impedance, low power standby mode is made by means of two resistance-capacitance (RC) networks.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 87% of the total text.

Variable Response, On Chip, Low Voltage Supply

      An on-chip three-volt power supply for the memory array portion
of a five-volt circuit design uses low standby power and has a fast,
accurate response to high current demands. A smooth transition from a
high current state back to high impedance, low power standby mode is
made by means of two resistance-capacitance (RC) networks.

      Referring to the figure, transistors T3, T8 and resistor R5
form a differential compare circuit which uses resistor R3 to control
transistor T9 and, therefore, output voltage V3 OUT.  When a current
demand is expected, a signal at PRE turns on transistors T1 and T4 to
prepare to reduce impedance of the compare circuit.  At the demand
time, nodes IN rise to 5 volts, turning on transistor T7 to reduce
the impedance of the output circuit controlling the gate of
transistor T9.  At the same time, the signal at nodes IN turns on
transistor T5, reducing the impedance of the compare circuit.  In
this low impedence state, the circuit is capable of delivering a
large current at V3 OUT.  A first RC network formed by resistor R1
and capacitor C1 and a second RC network formed by resistor R2 and
capacitor C2 also begin to discharge at the time of the signal on
nodes IN.  Resistor and capacitor values are selected such that the
output circuit controlling transistor T9 recovers to a high impedance
before the compare circuit to prevent output V3 OUT from overshooting
the final value.  Later,...