Browse Prior Art Database

Method for Making a Non-Planar Device Structure

IP.com Disclosure Number: IPCOM000102801D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 39K

Publishing Venue

IBM

Related People

Koburger, CW: AUTHOR [+3]

Abstract

By arranging to form a gate conductor on sidewalls of isolation trenches as well as on the usual planar top between trenches, current carrying capacity of transistors is increased without sacrificing device density.

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Method for Making a Non-Planar Device Structure

      By arranging to form a gate conductor on sidewalls of isolation
trenches as well as on the usual planar top between trenches, current
carrying capacity of transistors is increased without sacrificing
device density.

      Referring to Fig. 1, conventional processing is used to form
pad oxide 10 and pad nitride 12, form shallow isolation trenches in
silicon substrate 14, and form oxide passivation layer 16 over all
exposed silicon.  Next, thin nitride trench isolation liner 18 is
conformally deposited.  Then, silicon dioxide (SiO2) 20 is
conformally deposited and planarized to complete the cross section
shown in Fig. 1.

      Next, exposed nitride layers 12 and 18 are selectively etched
in hot phosphoric acid.  This etching procedure is continued to
remove nitride 18 to a distance down the trench sidewall, as shown.
Buffered hydrofluoric acid is used to remove oxide from silicon
substrate 14 which is not protected by nitride.  Then, gate oxide 22
is grown and gate conductor 24 is conformally deposited to form the
cross section shown in Fig. 2.  Conventional processing is used to
form line patterns in conductor 24 and to complete integrated
circuits.

      Disclosed anonymously.