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Browse Prior Art Database

AC Test Method

IP.com Disclosure Number: IPCOM000102819D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 63K

Publishing Venue

IBM

Related People

Diehl, CM: AUTHOR [+3]

Abstract

Disclosed is a method of AC testing at system clock speed Level-Sensitive Scan Design (LSSD) computer logic components, chips, modules, and cards which are not functionally bounded. The method is more closely related to system functionality than to static component test. The component could be divided into two sections - function and maintenance including test circuits. The AC test objective is to check whether a functional circuit performs to the design criteria. The maintenance circuit could be ignored.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

AC Test Method

      Disclosed is a method of AC testing at system clock speed
Level-Sensitive Scan Design (LSSD) computer logic components, chips,
modules, and cards which are not functionally bounded.  The method is
more closely related to system functionality than to static component
test.  The component could be divided into two sections - function
and maintenance including test circuits.  The AC test objective is to
check whether a functional circuit performs to the design criteria.
The maintenance circuit could be ignored.

      The basic idea of this disclosure is to apply pseudo random
input patterns at the primary inputs (component input pins) with the
maintenance input held to a system operation state.  The data inputs
could be random, since it should be any combination of bits.  The
control inputs could also be random since the function should react
to all possible combination of bits.  In case of an invalid bit
combination, the circuit should respond to indicate an illegal
request being made and a signal should reach its output.

      With the above assumption and expected response measured only
at the component outputs, the method of obtaining expected response
is to use a static simulator in the following way.  The sequence of
events at the input and output would be:
 1)  initialize array element via array test access method
(one-to-one correspondence).
      2)  initialize all SRL's (Scan Ring Latches) via LSSD
(Level-Sensitive Sc...