Browse Prior Art Database

Growable Register Array for High-Density CMOS Applications

IP.com Disclosure Number: IPCOM000102842D
Original Publication Date: 1990-Feb-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 42K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+2]

Abstract

Described is a technique providing a high-density solution for small, single-port arrays and a variety of multi-port array applications. In the large-logic chip environment, storage element macros may require special circuit implementation to incorporate some form of an array self-test. The described technique saves much of the area that would normally be devoted to enhance testability of these designs.

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Growable Register Array for High-Density CMOS Applications

      Described is a technique providing a high-density solution for
small, single-port arrays and a variety of multi-port array
applications.  In the large-logic chip environment, storage element
macros may require special circuit implementation to incorporate some
form of an array self-test.  The described technique saves much of
the area that would normally be devoted to enhance testability of
these designs.

      In Fig. 1, a Growable Register Array (GRA) consists of an array
of shift register latches (SRLs) 10.  The logic of the GRA is a
common implementation.  The WRITE address 20 gates the C-clock input
to select the proper cell during a write operation.  The outputs of
SRLs 10 are passed to a Multiplexor (MUX) 30 which uses a READ
address 40 to select the proper cell during a read access.  By
incorporating the MUX passgate as part of the storage cell,
significant layout advantages are attained.  Because the storage
elements are SRLs 10, full DC testability is possible.

      Fig. 2 shows a simple representation of the basic design.
Subsequent READ or WRITE ports are added by including the appropriate
passgates in the storage cell. Enhanced multiplexing is incorporated
to increase the design's address space capabilities.  Due to the
structured nature of this technique, algorithmic generation of these
circuits is easily accomplished.

      Disclosed anonymously.