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Improved Multi-Emitter Bicmos Logic Circuit

IP.com Disclosure Number: IPCOM000102862D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 32K

Publishing Venue

IBM

Related People

Kemerer, DW: AUTHOR

Abstract

Reduced reverse bias across emitter-base junctions of NPN pull-up transistors in BICMOS logic circuits, thus higher reliability, is achieved by this new circuit approach.

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Improved Multi-Emitter Bicmos Logic Circuit

      Reduced reverse bias across emitter-base junctions of NPN
pull-up transistors in BICMOS logic circuits, thus higher
reliability, is achieved by this new circuit approach.

      The figure shows a multi-emitter circuit to perform the logic
function TWO WAY AND INVERT.  When input A is high and input B is low
(or the reverse), the base of one pull-up NPN transistor T1 or T2 is
held at supply voltage VDD by its associated PMOS device T3 or T4.
Thus, the output and both pull-up emitters are caused to rise to
voltage V = VDD - Vbe, where Vbe is the base to emitter potential.
The base of the other NPN device is held to the lower of 1) the
output voltage or 2) the input voltage minus a threshold voltage Vt
of its associated NMOS input devices T5, T6, T7, T8, and T9.

      More complex logic circuits and opposite polarity circuits can
also benefit from the method shown here.

      Disclosed anonymously.