Browse Prior Art Database

Address Decoding for VALT

IP.com Disclosure Number: IPCOM000102884D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 40K

Publishing Venue

IBM

Related People

Kiessling, C: AUTHOR [+2]

Abstract

Disclosed is a method of reducing decode line congestion for designs using the VALT testing concept. The VALT concept requires direct addressing of each latch. Tester time reduction results from NOT being constrained to use sequential, contiguous strings of latches, but in using only the latches required for the test. Instead of implementing every individual control line for every VALT latch, an address register grouping concept is used to reduce the number of test lines required in the component design. Reduction will be in the range of from 4:1 to greater than 1000:1, dependent upon the size of the design.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Address Decoding for VALT

      Disclosed is a method of reducing decode line congestion for
designs using the VALT testing concept.  The VALT concept requires
direct addressing of each latch.  Tester time reduction results from
NOT being constrained to use sequential, contiguous strings of
latches, but in using only the latches required for the test.
Instead of implementing every individual control line for every VALT
latch, an address register grouping concept is used to reduce the
number of test lines required in the component design. Reduction will
be in the range of from 4:1 to greater than 1000:1, dependent upon
the size of the design.

      The achievement of the address line decongestion on the product
is accomplished by utilizing the value of bit groupings to achieve an
increase in addresses, i.e., the digits "111" have a binary value of
8, thus three digits provide 8 addresses.  The second three-digit
grouping would also provide 8 addresses.  The combination of the
results of these two groupings would provide 8 X 8 (64) addresses.
Thus, instead of 64 lines, 1 to each VALT, the use of only 16 lines
in combination one with another, and some final selection logic,
provides the same result.

      Disclosed anonymously.