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Frame Synchronizer With Parallel Logic for Detecting Location of a Sync Character And Logic Circuits for Realigning Data in Two Adjacent Frames

IP.com Disclosure Number: IPCOM000102892D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 79K

Publishing Venue

IBM

Related People

Chambers, RM: AUTHOR

Abstract

In some systems, a serial data character is transmitted in a frame of n bits that is converted to parallel at a receiving station. The n bits of each frame appear in a succession that does not distinguish one frame from the next, and synchronizing circuits at the receiving station identify the proper dividing point between frames. To begin communication, special sync characters are sent until the receiving station is in sync. When the frames are in sync at the receiving station, the n bits of a frame appear together in the parallel logic. If frames are out of sync, the n parallel bit positions have the ending bits of one frame and the beginning bits of the next frame.

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Frame Synchronizer With Parallel Logic for Detecting Location of a Sync Character And Logic Circuits for Realigning Data in Two Adjacent Frames

      In some systems, a serial data character is transmitted in a
frame of n bits that is converted to parallel at a receiving station.
The n bits of each frame appear in a succession that does not
distinguish one frame from the next, and synchronizing circuits at
the receiving station identify the proper dividing point between
frames.  To begin communication, special sync characters are sent
until the receiving station is in sync.  When the frames are in sync
at the receiving station, the n bits of a frame appear together in
the parallel logic.  If frames are out of sync, the n parallel bit
positions have the ending bits of one frame and the beginning bits of
the next frame.

      In this system, a conventional serial to parallel converter
produces units of n parallel bits without regard to synchronization.
These n bits are loaded into a first parallel n-bit register of the
synchronizing circuits.  As n bits from the converter are loaded into
the first register, the contents of the first register are
transferred to a second register.  If the station happens to be in
sync, the second register holds one complete frame and the first
register holds the next complete frame.  In the general case,
however, the first and second registers together hold one complete
frame, the end of the preceding frame, and the beginning of the next
frame.  The high order bit positions of the second register hold the
low order bits of the complete frame and the low order bit positions
of the first register hold the high order bits of this frame.  The
low order bit positions of the second register hold the high order
bits of a preceding frame, an...