Browse Prior Art Database

Overlapping Stores to Reduce Store-Fetch Interference in Caches

IP.com Disclosure Number: IPCOM000102915D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 33K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+6]

Abstract

An instruction which performs a single store uses the facilities associated with the cache on three distinct cycles. If these facilities are allocated jointly then the cache is unavailable for other accesses and this creates a performance deficit.

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Overlapping Stores to Reduce Store-Fetch Interference in Caches

      An instruction which performs a single store uses the
facilities associated with the cache on three distinct cycles.  If
these facilities are allocated jointly then the cache is unavailable
for other accesses and this creates a performance deficit.

      A store must perform a pretest at decode time, a lookup at
putaway time, and an update of the arrays.  For processors with a
"late select" capability, the lookup and update occur on different
cycles and, as such, create additional interference.

      The mechanism that is proposed is to eliminate the lookup step,
and to overlap the update step of a previous store with the pretest
step of the current store.  One versed in the art will observe that
the resources of the cache required to perform these steps are
complimentary and that both steps can be performed jointly if the
address that results from the pretest is retained and used during the
update step.  This portion of the mechanism is prior art; however,
the overlap of the update operation with a succeeding pretest
represents the novelty.

      Disclosed anonymously.