Browse Prior Art Database

Prefetching TM Targets to Resolve Branches Early

IP.com Disclosure Number: IPCOM000102916D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 45K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

A branch history table (BHT) will mispredict the action of a conditional branch instruction if the byte which is tested by the condition code generating instruction has been changed appropriately. Using a BHT which has been augmented to hold the putative address of the controlling byte and the information necessary to generate the condition code from that byte, the opportunity exists to prefetch the byte on the cycle after the BHT prefetches the instruction group that contains these instructions. Assuming that the putative target of the TM is correct, this action corresponds to an out-of-sequence fetch and for those designs which are sufficiently robust to allow for out-of-sequence operand accesses, the timing of the out-of-sequence action has been decoupled from the decoding action of the processor.

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This is the abbreviated version, containing approximately 87% of the total text.

Prefetching TM Targets to Resolve Branches Early

      A branch history table (BHT) will mispredict the action of a
conditional branch instruction if the byte which is tested by the
condition code generating instruction has been changed appropriately.
Using a BHT which has been augmented to hold the putative address of
the controlling byte and the information necessary to generate the
condition code from that byte, the opportunity exists to prefetch the
byte on the cycle after the BHT prefetches the instruction group that
contains these instructions.  Assuming that the putative target of
the TM is correct, this action corresponds to an out-of-sequence
fetch and for those designs which are sufficiently robust to allow
for out-of-sequence operand accesses, the timing of the
out-of-sequence action has been decoupled from the decoding action of
the processor.  No action associated with the prefetching of this
byte is required if the byte confirms the BHT prediction.  In the
case of a non-confirmation of the BHT, the suitable action can be
undertaken.  It is in this case that a performance advantage over a
BHT can be achieved.  The correct identification of a mispredicted
branch can, based on the earlier resolution provided by this
mechanism, eliminate the branch wrong guess penalty almost entirely.
An additional advantage of the proposed mechanism involves the cases
where the correct target causes a cache miss.  In an MP
configuration, such a miss might indicate the l...