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Using I-Cache to Promote D-Misses to Exclusive

IP.com Disclosure Number: IPCOM000102917D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 60K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

In multiprocessor systems involving caches an important aspect of cache control is the determination as to whether data lines are brought into the cache shared or exclusive. The premium on a correct decision can improve performance as shared residency for unmodified lines can reduce cache misses. However, additional time is required to promote a shared line to exclusive when a processor wants to modify a shared line.

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This is the abbreviated version, containing approximately 61% of the total text.

Using I-Cache to Promote D-Misses to Exclusive

      In multiprocessor systems involving caches an important aspect
of cache control is the determination as to whether data lines are
brought into the cache shared or exclusive. The premium on a correct
decision can improve performance as shared residency for unmodified
lines can reduce cache misses.  However, additional time is required
to promote a shared line to exclusive when a processor wants to
modify a shared line.

      The method detailed takes cognizance of the fact that the
intent to modify the line initially brought into the cache via a
fetch access may involve a store operation that can be near to or far
removed from the instruction that caused the initial cache miss.

      In the event of a cache miss caused by a fetch access of a
given instruction, a bit associated with that instruction, that is
maintained by the cache directory, is interrogated to determine the
status of the D-line on entry to the cache (Shared/Exclusive).  The
address of the instruction, to the required granularity, is
associated with the D-line just missed and the line is accessed with
the indicated status:
If the indicated line status is shared and is the
subject of
      a subsequent store operation the status of the line is
      changed to exclusive via the normal protocols.  This
pro  motion of the line to exclusive also changes the
(Shared/Exclusive) bit maintained by the cache
directory and
associated with...