Browse Prior Art Database

Nest Design for Flex

IP.com Disclosure Number: IPCOM000102919D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 47K

Publishing Venue

IBM

Related People

Horton, RR: AUTHOR [+3]

Abstract

This invention describes a nest suitable for holding a large silicon substrate (2.125 inches per side) used as a carrier for packaging an array of logic and memory chips in a C4 configuration and the flex necessary to join this carrier to the next level of package.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Nest Design for Flex

      This invention describes a nest suitable for holding a large
silicon substrate (2.125 inches per side) used as a carrier for
packaging an array of logic and memory chips in a C4 configuration
and the flex necessary to join this carrier to the next level of
package.

      The central concept of this location scheme revolves around
dead reckoning and the ability to make both the carrier and flex very
accurate and repeatable.  In the accompanying drawing the area
defined as chip nest is machined flat, square, and to a dimension of
.0007 inch larger per side than the carrier.  A slot designated chip
vacuum slot, is machined near the periphery and below the surface of
the nest area and is connected through an internal channel to the
pipe labeled chip vacuum pipe. While the nesting technique locates
the chip, the flex locating pin-holes will accept pins that mate with
holes in the flex and repeatedly place the flex coincidental with the
carrier.  On each side it should be noted that a slot runs between
the pin locating holes and is used to hold the flex flat and in
contact with the carrier.  Vacuum is applied to the carrier and then
to the flex to be joined and the two components are now ready for a
solder reflow to provide mechanical and electrical connections.

      Disclosed anonymously.