Browse Prior Art Database

Separate Set ID's And Late Selects for a Data Cache

IP.com Disclosure Number: IPCOM000102923D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 46K

Publishing Venue

IBM

Related People

Kahle, JA: AUTHOR

Abstract

This disclosure describes a way to prevent critical paths in a RISC architecture with a data cache. Separation of the set id's and the late selects also adds flexibility in the timings between load and store operations to the data cache.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 79% of the total text.

Separate Set ID's And Late Selects for a Data Cache

      This disclosure describes a way to prevent critical paths in a
RISC architecture with a data cache.  Separation of the set id's and
the late selects also adds flexibility in the timings between load
and store operations to the data cache.

      The late select control signals can be the most critical
signals in the system, since their path includes a double chip
crossing.  The data cache is four-way set associative.  The four late
select controls are used to choose one of the four sets during a load
operation.

      The set id's control signals do not have critical delays.  The
set id's represent the set in the data cache that the store data is
to be written in.  These lines are also used for unloading the Cache
Reload Buffer (CRB) into the data cache array, and loading the Store
Back Buffer (SBB) from the array.  Because the lines are not
critical, the set id's can be encoded in two lines representing one
of the four sets.

      Some data caches' designs have the late select and the set id
control signals combined into four non-encoded late select lines.
This configuration caused a number of problems.  With the new design,
the late selects are generated soley from the directory and compare
logic.  The set id control signals are generated from the pending
store queues.   This creates less delay in generating the late select
control signals.  The late selects need to be ready early in the...