Browse Prior Art Database

Late Stores for a Data Cache

IP.com Disclosure Number: IPCOM000102924D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 43K

Publishing Venue

IBM

Related People

Cocke, J: AUTHOR [+3]

Abstract

This disclosure describes a way to reduce the timing constraints on stores to a data cache. The late store data cache pipeline technique allows a store operation to occur over multiple cycles with minimal system performance impact.

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Late Stores for a Data Cache

      This disclosure describes a way to reduce the timing
constraints on stores to a data cache.  The late store data cache
pipeline technique allows a store operation to occur over multiple
cycles with minimal system performance impact.

      In some cache designs the store sequence is required to
complete by the end of the fixed point write back (or cache access
cycle).  This would require that the data and late selects be sent
over to the data cache during the first part of the cache access
cycle.  The data would be written into the array during the last part
of the data cache array. This would require that the data drivers
from the fixed point be quick enough to send the data between the
chips in less than half of a cycle.  This could create a greater chip
current switching problem with the chip buses because the drivers
would have to be very fast.

      With a late store technique, there is more time to complete the
store operation.  The data from the fixed/floating point chips are
sent over during the write back (or cache access cycle) of the fixed
point chip.  The store is then written into the array the next time
the array is not servicing a load.  This allows for a complete cycle
for the data to be transferred from the fixed/floating point chips to
the data cache.

      The figure illustrates the differences in timings between the
two approaches.

      Disclosed anonymously.