Browse Prior Art Database

Bidirectional Bus Network

IP.com Disclosure Number: IPCOM000102926D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 36K

Publishing Venue

IBM

Related People

Oakland, SF: AUTHOR

Abstract

By combining a shift register latch with a three-state bus, the high impedance state of the bus is avoided. During test, the latch provides termination to the bus, allowing observations of faults in driver enable logic. The latch also allows scan path access to the bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Bidirectional Bus Network

      By combining a shift register latch with a three-state bus, the
high impedance state of the bus is avoided.  During test, the latch
provides termination to the bus, allowing observations of faults in
driver enable logic.  The latch also allows scan path access to the
bus.

      Referring to the figure, bidirectional bus 30 is driven by one
of any number of bus drivers, e.g., 1-4, or bus latch 5.  Bus driver
selector logic 6 activates no more than one signal line 7, 8, 9, or
10.  When a pulse is applied to clock line 11, selected data 31-34 is
driven onto bidirectional bus 30.  For example, when enable signal
line 8 is selected and clock line 11 is pulsed, data 32 is driven
onto bus 30.

      When clock line 11 is inactive, or when all enable lines 7-10
are inactive, bidirectional bus 30 retains the signal that was last
driven onto it.  This signal retention may be accomplished with weak
feedback devices in bus latch 5.

      When scan clock(s) 15 is pulsed, data on bus 30 may be observed
at scan data output 20 and input scan data 16 is driven onto bus 30
by bus latch 5.

      Disclosed anonymously.