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Minimal Device Programmable Growable LSSD Up-Down Counter

IP.com Disclosure Number: IPCOM000102978D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 42K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+2]

Abstract

The figure illustrates a minimal device count, growable, and programmable LSSD up-down counter. The schematic is for one bit of the counter. The inputs and outputs are defined.

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Minimal Device Programmable Growable LSSD Up-Down Counter

      The figure illustrates a minimal device count, growable, and
programmable LSSD up-down counter.  The schematic is for one bit of
the counter.  The inputs and outputs are defined.

      Each bit's latch is connected in a toggle fashion.  An L2
signal is routed back to a -Data input.  An LD signal initializes the
counter to the value on node -D1.  Devices o,p,q,r are used to force
the starting point of the counter based on signal SS1.  If SS1 is a
0, the counter starts at all 0s.  If SS1 is a 1, the counter starts
at the complement of the programmed bits (In).  The counter is always
counting up internally, but devices s-z are used to gate the inverse
of L2 or NL2 to the counter outputs (On).  If L2 is gated to the
output (SS1=1), then the counter looks like it is counting down at
its outputs.  The C-clock input for the first bit is the system
C-clock.  The C-clock inputs for the remaining bits are gated by the
output of the counter bit previous to them, devices 1-6.  Each bit of
the counter has an identical device configuration, enabling the
counter to be grown to any size desired.

      Disclosed anonymously.