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Protected Error Handling for Microprocessor-Based Systems

IP.com Disclosure Number: IPCOM000102985D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 53K

Publishing Venue

IBM

Related People

Fawcett, BW: AUTHOR [+2]

Abstract

A method is described which protects critical exception handlers in a microprocessor system from being corrupted from errant writes while still allowing them to be changed as needed. A combination of read-only storage (ROS) and random-access memory (RAM) storage is utilized to provide this capability.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 85% of the total text.

Protected Error Handling for Microprocessor-Based Systems

      A method is described which protects critical exception
handlers in a microprocessor system from being corrupted from errant
writes while still allowing them to be changed as needed.  A
combination of read-only storage (ROS) and random-access memory (RAM)
storage is utilized to provide this capability.

      When the microprocessor detects that an exception has occurred,
it invokes an appropriate exception handler, accessed through an
exception handler vector table.  In the figure, this vector table 1
and primitive exception handlers 2 both reside in ROS.  Placing these
items into ROS guarantees that the primitive exception handling
capability is immune to errant writes.

      In order to provide the flexibility of installing new exception
handlers, ROS exception handler 2 has a provision within it to access
a secondary exception handler vector table 3 that resides in RAM.
When a program wants to install a new exception handler 4, it places
a pointer to it into the RAM vector table 3.  ROS exception handler
2, when invoked, then checks to see if a RAM exception handler 4 was
installed into RAM vector table 3, and if so, passes control to it
instead.

      ROS exception handler 2 does not blindly jump to RAM exception
handler 4, or all of the immune advantages are lost.  Prior to any
invocation of RAM exception handler 4, ROS exception handler 2
performs some validity checks against both...