Browse Prior Art Database

Clocks On Sequencing for Controlled Parity Checking

IP.com Disclosure Number: IPCOM000102986D
Original Publication Date: 1990-Apr-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 37K

Publishing Venue

IBM

Related People

Douskey, SM: AUTHOR [+2]

Abstract

Described is a technique which controls interchip parity checking after clocks are initially applied. When clocks are applied to an inner machine processor interface processor, all interchip control busses do NOT have valid parity. Parity checkers are enabled only after the processor reaches a known state. The described technique addresses this problem.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Clocks On Sequencing for Controlled Parity Checking

      Described is a technique which controls interchip parity
checking after clocks are initially applied.  When clocks are applied
to an inner machine processor interface processor, all interchip
control busses do NOT have valid parity.  Parity checkers are enabled
only after the processor reaches a known state.  The described
technique addresses this problem.

      "System clocks" to all latches are gated by latched "clocks on"
signals.  Refer to the figure.  A free-running latch is added named
"EnableP" (for enable parity).  A clock for this latch is not under
control of the "clocks on" signal.  The latched "clocks on" signal is
the data input to the "EnableP" latch.  "EnableP" is active on the
second cycle after clocks are on and stays active until the first
cycle after clocks are off.  Parity is checked on appropriate
interchip latched data busses only when EnableP is active.

      Disclosed anonymously.