Browse Prior Art Database

Fast "AND" Slow "OR" Circuit for Logical Dotting

IP.com Disclosure Number: IPCOM000103004D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 52K

Publishing Venue

IBM

Related People

Hovis, WP: AUTHOR [+2]

Abstract

This circuit combines the advantages of AND and OR circuits for dotting independently timed memory arrays while taking care of problems in the use of one or the other of these logic circuits for all good or partially good chip programs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 81% of the total text.

Fast "AND" Slow "OR" Circuit for Logical Dotting

      This circuit combines the advantages of AND and OR circuits for
dotting independently timed memory arrays while taking care of
problems in the use of one or the other of these logic circuits for
all good or partially good chip programs.

      Referring to the circuit diagram, a slow OR circuit is
comprised of a standard NOR, transistors T2, T4, T6, and T8, followed
by an inverter, transistors T10 and T12. Transistors T14, T16, T18,
and T20 are used to perform the fast AND function.  Whereas a stack
of two devices alone would have been sufficient to perform the
necessary logic, the circuit shown insures that the effective delay
from input INA and/or INB to output OUT is always the same.  The AND
devices have width dimension sufficiently large to pull node A down
quickly if both inputs INA and INB become active, thus allowing
output OUT to go high quickly. Transistors T2 and T4 are made weaker
(narrower or shorter) thus, with only one input INA or INB becoming
active, node A discharges slowly and the high output OUT is delayed.
This technique can be extended to more than two inputs and can be
implemented in technologies other than complementary metal oxide
silicon (CMOS).

      If the inputs are skewed by less than the delay between one and
two inputs going active, then when the later input becomes active,
node A goes low quickly and output OUT goes high quickly.  Thus,
independently timed quadrants with...