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Circuit Speed Detection And Control Method

IP.com Disclosure Number: IPCOM000103005D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 44K

Publishing Venue

IBM

Related People

Adams, RD: AUTHOR [+2]

Abstract

To keep an integrated circuit chip running at a design speed, two oscillators are provided. The first oscillator is constructed with devices having very short effective channel length and the second oscillator is made with long channel length devices. The first oscillator has a period or frequency which varies according to process variations affecting channel length, and the second oscillator has a period affected very little by channel length variation. Variation in difference between the two oscillator periods is used to add appropriate delay in fast chips, thereby bringing all circuits on all chips to a specified performance level.

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Circuit Speed Detection And Control Method

      To keep an integrated circuit chip running at a design speed,
two oscillators are provided.  The first oscillator is constructed
with devices having very short effective channel length and the
second oscillator is made with long channel length devices.  The
first oscillator has a period or frequency which varies according to
process variations affecting channel length, and the second
oscillator has a period affected very little by channel length
variation. Variation in difference between the two oscillator periods
is used to add appropriate delay in fast chips, thereby bringing all
circuits on all chips to a specified performance level.

      Referring to the figure, long channel oscillator 2 is designed
to have a period P much longer than the period p of short channel
oscillator 4, e.g., P = 100p.  Enable input IN starts and maintains
operation of the speed detection circuitry.  Reset logic 6 acts at
turn-on to reset counter 8.  Then, counter 8 takes the output from
NAND gate 10 until reset logic 6 and transfer logic 14 sense the end
of one period from oscillator 4.  Latch 12 is then set to select an
appropriate delay in the circuitry to be controlled, shown as slow S,
medium M, and fast F output from speed control circuit 12.  Counter 8
is then reset.

      Enable input IN may be turned off after latch 12 is set or
remain on to continuously check and compensate for speed changes
taking place due to volt...