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Switched Pull-Down Base Drive for BICMOS

IP.com Disclosure Number: IPCOM000103007D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 32K

Publishing Venue

IBM

Related People

Reynolds, CB: AUTHOR

Abstract

Performance of bipolar, complementary, metal, oxide, silicon (BICMOS) logic circuits is enhanced by using one or more pass transistors to gate current into the base of an output pulldown transistor, thus reducing output pulldown delay.

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Switched Pull-Down Base Drive for BICMOS

      Performance of bipolar, complementary, metal, oxide, silicon
(BICMOS) logic circuits is enhanced by using one or more pass
transistors to gate current into the base of an output pulldown
transistor, thus reducing output pulldown delay.

      Referring to the figure, n-type transistors T1, T2, and T3 are
added to a standard BICMOS two way NAND circuit to provide current
from inputs A or B to the base of bipolar pulldown transistor T4 when
transistor T1 is gated on by output OUT.  As pulldown transistor T4
nears saturation and voltage of input A or B rises to within a
threshold voltage (Vt) of T1, pass transistor T1 is shut off and
conventional circuit operation continues.

      Pass devices of types other than n-MOS may be used to obtain
the significant reduction in pulldown delay in this NAND circuit as
well as in other BICMOS logic circuits.

      Disclosed anonymously.