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Browse Prior Art Database

Frequency Multiplier

IP.com Disclosure Number: IPCOM000103028D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 35K

Publishing Venue

IBM

Related People

Boerstler, DW: AUTHOR

Abstract

Disclosed is a technique for frequency multiplication of a reference clock which does not require a phase-locked loop with a divider in the feedback loop. The technique involves cascading a series of DELAY/EX-OR stages which can be configured to generate any power of two (2**N, where N=1, 2, 3, ...) multiplication factor from a reference clock with period T. (See Fig. 1).

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Frequency Multiplier

      Disclosed is a technique for frequency multiplication of a
reference clock which does not require a phase-locked loop with a
divider in the feedback loop.  The technique involves cascading a
series of DELAY/EX-OR  stages which can be configured to generate any
power of two (2**N, where N=1, 2, 3, ...) multiplication factor from
a reference clock with period T.  (See Fig. 1).

      Each DELAY/EX-OR stage 12 is constructed of an exclusive-or
gate 14 with a fixed delay element 16 between its two inputs.  One of
the inputs to the EX-OR gate is used as the input 18 to the stage,
and the EX-OR's output is the output 20 of the stage.  N of these
DELAY/EX-OR stages are cascaded so that the input of each stage is
connected to the output of the immediately preceding stage, with the
input of the first stage connected to the reference clock 10 and the
output 22 of the last stage used as the frequency-multiplied
reference.  The value of the delay element used for each stage is
selected to be one-half of the value of the delay in the immediately
preceding stage, with the first and last stages having delays of T/4
and T/(2**(N+1)), respectively.

      Disclosed anonymously.