Browse Prior Art Database

Means of Increasing Yield On Logic Chips

IP.com Disclosure Number: IPCOM000103077D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-17
Document File: 1 page(s) / 47K

Publishing Venue

IBM

Related People

Tuttle, DP: AUTHOR

Abstract

In some logic chips there is spare area not utilized. Many times the silicon die size is determined by the pin count requirements instead of area required for logic functions. In such cases the spare silicon area could be used to replicate a portion of the logic function. By having configurable fuses on the chip in a similar fashion to the way fuses are implemented for redundant word lines of array macros the redundant logic could be used by the logic chip. Major functions of the original chip could be defective and the chip still could be wholly functional once the spare logic is enabled. This can be done by dotting OCD's (Off Chip Drivers) at the output of the chip or by having an additional multiplexor function added to a section of the main section of the logic.

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Means of Increasing Yield On Logic Chips

      In some logic chips there is spare area not utilized.  Many
times the silicon die size is determined by the pin count
requirements instead of area required for logic functions. In such
cases the spare silicon area could be used to replicate a portion of
the logic function.  By having configurable fuses on the chip in a
similar fashion to the way fuses are implemented for redundant word
lines of array macros the redundant logic could be used by the logic
chip. Major functions of the original chip could be defective and the
chip still could be wholly functional once the spare logic is
enabled.  This can be done by dotting OCD's (Off Chip Drivers) at the
output of the chip or by having an additional multiplexor function
added to a section of the main section of the logic.  The main and
redundant logic would be designed so that their respective OCD's
would be tri-state if the fuse information did not indicate that
their respective logic should be enabled so that the OCD's do not
conflict.

      In the case where an additional multiplexor function was added
to utilize the functional main or redundant logic, the fuse
information would be used to select the proper port of the
multiplexor.

      This scheme without an internal fuse could be used in a system
which required high availability.  An external pin or additional
logic could be used to reconfigure the chip to select the redundant
logic once a fault has been d...